IBM Corporation, Applied Materials, Inc. and the College of Nanoscale Science and Engineering (CNSE) of the University at Albany (UAlbany NanoCollege) announced an agreement to jointly develop process modeling technology for manufacturing 22 nanometer (nm) logic and memory chips.

The project will combine IBM’s semiconductor technology research and development leadership and computer modeling expertise with Applied’s semiconductor processing knowledge to develop predictive models that can help minimize process variation, reduce development cost, and improve time to market for 22nm semiconductors.

FinFET transistors – vertical transistors with fin-shaped silicon channels – will be used to validate the technology. FinFETs are considered a potential successor to conventional planar transistors for 22nm chips.

Today’s most advanced semiconductors have circuitry at 45 nanometers and larger. Producing circuits at 22nm becomes more challenging since current lithography methods – the process for creating circuit patterns on silicon wafers – present physical limitations for critical chip layers. To help overcome these limitations, IBM has led an initiative known as Computational Scaling. Computational-based processes developed by IBM use advanced mathematical techniques, software tools and high-performance computing systems to enable the production of complex, powerful and energy-efficient semiconductors at 22 nanometers and beyond.