Dave Savastano10.30.14
imec has announced a joint development project with Coventor, a leading supplier of semiconductor process development tools. The collaboration will enable faster and more optimized development of advanced manufacturing technology in the 3D device architecture era, extending down to imec’s 10- and 7-nanometer (nm) processes.
To adopt the 7nm node, the industry needs to select the optimal layout, as well as optimize process step performance and control methodology. Using Coventor’s SEMulator3D platform, engineers from imec and Coventor are working together to reduce silicon learning cycles and development costs by down selecting the options for development of next-generation manufacturing technologies.
At imec, process and integration experts have connected optical lithography simulations with Coventor’s SEMulator3D virtual fabrication platform to explore FinFET scaling to the 7nm node and to compare the process window marginalities in several dense SRAM designs using Spacer Assisted Quadruple Patterning and either multiple immersion or EUV patterning cut/keep solutions.
“A virtual fabrication platform enables us to tie together integrated processing before all of the individual processes are available,” An Steegen, senior vice president process technology at imec said. “The SEMulator3D tool gives us the visibility and accuracy to do that, and an integrated platform to bring together all the various elements of advanced processing before moving on to actual silicon.”
“This collaboration allows us to synchronize our modeling roadmap with one of the industry’s most advanced process roadmaps, as well as to speed the development of their 10nm and 7nm technology,” said David Fried, chief technical officer, Semiconductor, at Coventor. “Working together with imec on novel integration schemes, designing SEMulator3D-specific structures for imec’s testsites, and then calibrating advanced models to imec’s wafer processing is an extremely effective and valuable way for Coventor to optimize our virtual fabrication platform for emerging market requirements.”
To adopt the 7nm node, the industry needs to select the optimal layout, as well as optimize process step performance and control methodology. Using Coventor’s SEMulator3D platform, engineers from imec and Coventor are working together to reduce silicon learning cycles and development costs by down selecting the options for development of next-generation manufacturing technologies.
At imec, process and integration experts have connected optical lithography simulations with Coventor’s SEMulator3D virtual fabrication platform to explore FinFET scaling to the 7nm node and to compare the process window marginalities in several dense SRAM designs using Spacer Assisted Quadruple Patterning and either multiple immersion or EUV patterning cut/keep solutions.
“A virtual fabrication platform enables us to tie together integrated processing before all of the individual processes are available,” An Steegen, senior vice president process technology at imec said. “The SEMulator3D tool gives us the visibility and accuracy to do that, and an integrated platform to bring together all the various elements of advanced processing before moving on to actual silicon.”
“This collaboration allows us to synchronize our modeling roadmap with one of the industry’s most advanced process roadmaps, as well as to speed the development of their 10nm and 7nm technology,” said David Fried, chief technical officer, Semiconductor, at Coventor. “Working together with imec on novel integration schemes, designing SEMulator3D-specific structures for imec’s testsites, and then calibrating advanced models to imec’s wafer processing is an extremely effective and valuable way for Coventor to optimize our virtual fabrication platform for emerging market requirements.”