The approach includes two scenarios for EUVL insertion that, when combined with an array of scaling boosters, serve as a basis of the industry requirements for power, performance, area and cost. Including proposals for design rules, masks, photoresists, etching and metrology and an extensive process variation assessment, imec’s R&D has established the first comprehensive solution for EUVL enablement in high-volume manufacturing.
As an alternative to the cost-prohibitive and complex self-aligned quadruple patterning (SAQP) + immersion triple block patterning for the 32nm metal layer (M2), imec has developed two approaches that include exposure on ASML’s NXE:3300B EUV-scanner.
The primary solution involves completing the SAQP with a single EUV blocking step, which offers a 20% wafer cost reduction over the full immersion approach. The alternate approach relies on EUV for a single patterning step, replacing both the SAQP and triple blocking steps. This adds an additional cost reduction, but has more implementation challenges than the SAQP+EUV block solution.