Brewer Science, Inc. announced its participation in SEMICON Taiwan 2017. The company will share in a knowledge exchange about semiconductor-manufacturing trends in Taiwan that are emerging in both front- and back-end materials, and process steps for next-generation manufacturing.
 
Today’s consumer electronics, networking, high-performance computing (HPC) and automotive applications rely on semiconductor devices that offer more performance and functionality while generating less heat and operating at lower power, all packed into a small form factor.
 
Leading foundries and integrated device manufacturers (IDMs) continue to push the limits of device scaling beyond 7 nm toward 3 nm, with Moore’s law driving front-end process development. At the same time, all eyes are on the innovative advanced- packaging approaches being developed by outsourced semiconductor assembly and test (OSAT) companies that are offering another very strong approach to achieving these requirements.
 
Brewer Science recognizes that the industry needs the high computing power that can only be achieved through advanced node logic and memory, as well as the heterogeneous-integration capabilities that require advanced-packaging innovations. The company has invested in developing specialty materials and processes that support both, from its robust portfolio of temporary bond/debond materials and processes for fan-out packaging (FO) and 3D IC manufacturing processes to its EUV and DSA materials for advanced lithography processes.
 
Taiwan’s semiconductor-manufacturing industry is committed to advanced-node lithography as well as the high-volume manufacturing (HVM) of advanced wafer-level packaging. Additionally, the region has a strong display-industry infrastructure.
 
“Taiwan’s leading-edge foundries, research institutes and OSATs have always been highly regarded as leaders in semiconductor manufacturing,” said Dr. Terry Brewer, president and CEO, Brewer Science. “We are committed to supporting Taiwanese innovation, from device design through high-volume manufacturing, with leading-edge material sets and processes that address the supply chain needs of both front-end silicon and back-end advanced wafer-level packaging architectures.”
 
Back-end Trends
 
Discussions surrounding FO architectures, at both the wafer and panel levels, are dominating the packaging scene for system-in-package and heterogeneous-integration applications. The focus is primarily on the chips-first approach, which has been in production for almost nine years, and the RDL-first approach, which is targeted at more advanced architectures. Both must accommodate more die in the same package, which is increasing stress and contributing to wafer bow. This calls for temporary carrier support throughout the process. Additionally, while not yet adopted into manufacturing, OSATs are gearing up for FO panel-level processes (FO-PLP).
 
Adoption of these approaches is driving interest in laser-release debond approaches that are suited to glass-substrate support processes for RDL first and FO-PLP. Brewer Science’s latest generation of debond materials is designed for laser release.
 
“In Taiwan, we are working closely with research institutes and OSATs to implement both our wafer- and panel-level bonding materials in all approaches to FO, as well as 2.5D and 3D integration schemes,” said Jim Lamb, deputy CTO, Brewer Science.
 
Brewer Science CTO Dr. Tony Flaim presented the company’s latest wafer bond/debond solutions for advanced packaging during SEMI’s co-located 3D Technology Forum on, Sept. 14.
 
Front-end Trends
 
Leading-edge manufacturing is now at 10 nm, with dimensions under 10 nm and beyond not far off now that the extreme ultraviolet (EUV) lithography process is becoming a reality. Many companies have committed to a roadmap that extends beyond 3 nm.
 
Directed self-assembly (DSA), in which the material itself forms the lithography pattern, is a paradigm shift in lithography that complements EUV. Best suited for devices with multiple, repeating, regular fine-pitch features, DSA can achieve 30-nm feature sizes without requiring additional masks. EUV can be used to pattern lower-resolution features on a wafer and create spacers for subsequent DSA deposition.
 
“While still in its developmental stages, DSA is on target to be production-ready within two years,” said Lamb. “Together, DSA and EUV offer a complementary set of benefits for IDMs and foundries to advance their manufacturing capabilities. Taiwanese manufacturers are leading the way with continued scaling efforts that comprise both DSA and EUV technologies.”
 
Lamb delivered a presentation titled Extending Lithography with Advanced Materials and Manufacturing Excellence during SEMI’s IC Forum at SEMICON Taiwan, on Sept. 15.