04.25.22
Applied Materials, Inc. introduced innovations that help customers continue 2D scaling with EUV and detailed the industry’s broadest portfolio of technologies for manufacturing next-generation 3D Gate-All-Around transistors.
Chipmakers are pursuing two complementary paths to increase transistor density in the years ahead. One is classic Moore’s Law 2D scaling, creating smaller features using EUV lithography and materials engineering.
The other is using design technology cooptimization (DTCO) and 3D techniques that optimize the layout of logic cells to increase density independent of changes in the lithography pitch. These latter approaches, which include backside power distribution networks and Gate-All-Around (GAA) transistors, are expected to drive a growing proportion of logic density improvements in future years as classic 2D scaling slows.
Together, these techniques can help chipmakers as they aim to deliver future generations of logic chips with improved power, performance, area, cost and time-to-market – or PPACt.
“Applied’s strategy is to be the PPACt enablement company for our customers, and today we are presenting seven innovations designed to enable customers to continue 2D scaling with EUV,” said Dr. Prabu Raja, SVP and GM of the Semiconductor Products Group at Applied Materials. “We are also detailing how GAA transistors will be manufactured in fundamentally different ways than today’s Fin- FET transistors, and how Applied is ready with the broadest product line for GAA manufacturing including new steps in epitaxy, atomic layer deposition and selective materials removal along with two new Integrated Materials Solutions for creating ideal GAA gate oxides and metal gates.”
The emergence of extreme ultraviolet (EUV) lithography has enabled chipmakers to produce smaller features and increase transistor density. However, the industry has reached a point where further scaling with EUV is introducing challenges that require new approaches to deposition, etch and metrology.
Following EUV resist development, chip patterns need to be etched through a series of intermediate layers – called the transfer layer and hardmask – before they are finally etched into the wafer. Until now, these layers have been deposited using spin-on technology.
Applied is introducing the Stensar Advanced Patterning Film for EUV which is deposited using Applied’s Precision CVD (chemical vapor deposition) system. Compared to spin-on deposition, Applied’s CVD film helps customers tune the EUV hardmask layers for specific thicknesses and etch resiliency so they can achieve near-perfect EUV pattern transfer uniformity across the entire wafer.
Applied also detailed a special capability of its Sym3 Y etch systems which enables customers to etch and deposit materials in the same chambers to help improve EUV patterns before they are etched into the wafer.
Applied also demonstrated how its PROVision eBeam metrology technology can be used to see deeply within multilayer chips to precisely measure EUV-patterned features across the entire wafer, helping customers solve “edge placement errors” that other metrology techniques cannot diagnose. Applied nearly doubled its eBeam system revenue in 2021 and has become the number-one supplier of eBeam technology.
A major challenge of manufacturing GAA transistors is that the space between the channels is only around 10nm, and customers must deposit the multilayer gate oxide and metal gate stacks around all four sides of the channels in the minute space available.
Applied has developed an IMS (Integrated Materials Solution) system for the gate ox-ide stack. A thinner gate oxide results in higher drive current and transistor performance.
However, thinner gate oxides typically result in higher leakage current that wastes power and creates heat. Applied’s new IMS system reduces equivalent oxide thickness by 1.5 angstroms, enabling designers to increase performance with no increase in gate leakage or keep performance constant and reduce gate leakage by more than 10X. It integrates atomic layer deposition (ALD), thermal steps, plasma treatment steps and metrology in a single, high-vacuum system.
Chipmakers are pursuing two complementary paths to increase transistor density in the years ahead. One is classic Moore’s Law 2D scaling, creating smaller features using EUV lithography and materials engineering.
The other is using design technology cooptimization (DTCO) and 3D techniques that optimize the layout of logic cells to increase density independent of changes in the lithography pitch. These latter approaches, which include backside power distribution networks and Gate-All-Around (GAA) transistors, are expected to drive a growing proportion of logic density improvements in future years as classic 2D scaling slows.
Together, these techniques can help chipmakers as they aim to deliver future generations of logic chips with improved power, performance, area, cost and time-to-market – or PPACt.
“Applied’s strategy is to be the PPACt enablement company for our customers, and today we are presenting seven innovations designed to enable customers to continue 2D scaling with EUV,” said Dr. Prabu Raja, SVP and GM of the Semiconductor Products Group at Applied Materials. “We are also detailing how GAA transistors will be manufactured in fundamentally different ways than today’s Fin- FET transistors, and how Applied is ready with the broadest product line for GAA manufacturing including new steps in epitaxy, atomic layer deposition and selective materials removal along with two new Integrated Materials Solutions for creating ideal GAA gate oxides and metal gates.”
The emergence of extreme ultraviolet (EUV) lithography has enabled chipmakers to produce smaller features and increase transistor density. However, the industry has reached a point where further scaling with EUV is introducing challenges that require new approaches to deposition, etch and metrology.
Following EUV resist development, chip patterns need to be etched through a series of intermediate layers – called the transfer layer and hardmask – before they are finally etched into the wafer. Until now, these layers have been deposited using spin-on technology.
Applied is introducing the Stensar Advanced Patterning Film for EUV which is deposited using Applied’s Precision CVD (chemical vapor deposition) system. Compared to spin-on deposition, Applied’s CVD film helps customers tune the EUV hardmask layers for specific thicknesses and etch resiliency so they can achieve near-perfect EUV pattern transfer uniformity across the entire wafer.
Applied also detailed a special capability of its Sym3 Y etch systems which enables customers to etch and deposit materials in the same chambers to help improve EUV patterns before they are etched into the wafer.
Applied also demonstrated how its PROVision eBeam metrology technology can be used to see deeply within multilayer chips to precisely measure EUV-patterned features across the entire wafer, helping customers solve “edge placement errors” that other metrology techniques cannot diagnose. Applied nearly doubled its eBeam system revenue in 2021 and has become the number-one supplier of eBeam technology.
A major challenge of manufacturing GAA transistors is that the space between the channels is only around 10nm, and customers must deposit the multilayer gate oxide and metal gate stacks around all four sides of the channels in the minute space available.
Applied has developed an IMS (Integrated Materials Solution) system for the gate ox-ide stack. A thinner gate oxide results in higher drive current and transistor performance.
However, thinner gate oxides typically result in higher leakage current that wastes power and creates heat. Applied’s new IMS system reduces equivalent oxide thickness by 1.5 angstroms, enabling designers to increase performance with no increase in gate leakage or keep performance constant and reduce gate leakage by more than 10X. It integrates atomic layer deposition (ALD), thermal steps, plasma treatment steps and metrology in a single, high-vacuum system.
