GAA nanowire transistors are promising candidates to succeed FinFETs in 7nm and beyond technology nodes. They offer optimal electrostatic control, thereby enabling ultimate CMOS device scaling. In a horizontal configuration, they are a natural extension of today’s mainstream FinFET technology. In this configuration, the drive current per footprint can be maximized by vertically stacking multiple horizontal nanowires. Earlier this year, imec scientists demonstrated GAA FETs based on vertically stacked 8nm diameter Si nanowires. These devices showed excellent electrostatic control, but were fabricated for n- and p-FETs separately.
Imec now reports on the CMOS integration of vertically stacked GAA Si nanowire MOSFETs, with matched threshold voltages for n- and p-type devices.
“GAA nanowire transistors enable ultimate CMOS device scaling, with low degree of added complexity compared to alternative scaling scenarios,” stated Dan Mocuta, director logic device and integration at imec.