With the continued scaling of advanced process nodes, the impact of parasitic interconnect resistance on the switching delay of standard cells rises considerably.
The new model developed through this collaboration enables the evaluation of interconnect material and process options through simulations in the early stages of technology development, when wafer data is not available, and in the process optimization and integration stages of technology development, where it reduces expensive and time-consuming wafer-based iterations.
“We have already released to our partners a number of sets of model parameters related to various liner/barrier systems for Cu metallization or to alternative metals, such as Ru and Co, which they will use to screen metallization options for next-generation interconnect technologies,” said Dan Mocuta, director, Logic Device and Integration at imec.
To use the new resistivity model, customers simulate the fabrication of the interconnect structure in 3D using the Synopsys process emulation tool Process Explorer, and then simulate the wire and via resistance in Raphael, the Synopsys interconnect field solver.
Imec has calibrated the resistivity model to wafer data for Cu, W, Ru and Co interconnects.