3D-ICs exploit the vertical dimension for further integration by stacking dies on top of each other – as a way of keeping the momentum of Moore’s Law going.
“Advances in wafer processing and stack assembly technologies are creating a wealth of different stack architectures,” said Eric Beyne, fellow and program director 3D System Integration at imec. “This causes a sharp increase in the number of potential moments at which testing for manufacturing defects can be executed: pre-bond (before stacking), mid-bond (on partial stacks), post-bond (on complete stacks), and final test (on packaged 3D-ICs). Test equipment contacts ICs via its external interface through probe needles or at test socket. In a die stack, that external interface typically resides in the bottom die of the stack. For the test equipment to be able to deliver test stimuli to and receive responses from the various dies up in the stack, collaboration from the underlying dies is required to provide test access to the die currently being tested.”
An IEEE working group to standardize 3D-DfT was founded in 2011 by Erik Jan Marinissen, scientific director at imec in Leuven, Belgium and he served as its first chair. In recent years, Adam Cron, principal R&D engineer in the Design Group at Synopsys, has been the driving force as the current chair of the Working Group.
“3D-IC is an important technology to deliver the next wave of innovation as the industry scales past 7nm. Currently, die might come from different suppliers with disjoint DfT ar-chitectures,” added Amit Sanghani, VP of engineering in the Design Group at Synopsys in Mountain View, CA. "We believe standardizing 3D-DfT will benefit our customers by help-ing form a consistent stack-level DfT architecture and speeding time to market.”